The present invention relates generally to data clock recovery circuits and, more particularly, to such circuits for recovering clock over a wide frequency of NRZ data.
For a communications link to receive data, it must first recover the clock rate at which the data is arriving. Typically, the incoming digital data format may be of the non return to zero (NRZ) type. NRZ digital data generally refers to a binary code form having two states, "zero" and "one", with no neutral state: information may be contained in the state of the waveform. When NRZ data formats are used there may be very little clock signal energy in the data signal and, thus, a phase lock loop (PLL) circuit may often be necessary to recover the data. If the data rate of the incoming signal can vary only by about .+-.1%, the PLL can usually acquire lock by itself. If the data rate can vary by as much as .+-.30%, a frequency comparator coupled with the PLL may be necessary to acquire lock. However, if the data rate is random or varies by significantly more than this, say, for example, by a ratio of 350 to 1, then frequency comparator-PLL devices are no longer sufficient because, for example, there are inherent ambiguities between data rates that are multiples of each other. For example, such devices cannot determine the difference between a 1010 data code at a 1 MHz frequency and a 11001100 data code at a 2 MHz frequency. In such circumstances, it becomes necessary to provide additional information to the clock recovery circuit in order to acquire lock.
Typically, prior data transmission systems have had to operate at a single clock rate or at a limited number (perhaps seven or eight) of standard clock rates due to the difficulty of recovering clock signals from data signals which vary over a wide range of frequencies. In this case, additional information in the form of a specifically defined selection of data rates may be provided by switch-selected inductors or crystals to enable clock recovery. Unfortunately, if the number of possible data frequencies becomes large, the number of necessary inductors or crystals would render the circuit impractical.
The present invention solves this problem by creating a continuously variable crystal, in the form of a frequency synthesizer. Prior wide range frequency synthesizers have often required direct frequency synthesis or multi-loop realization, both of which involve much signal mixing and filtering and would further complicate the clock recovery circuit. Attempts to provide clock recovery circuits with single loop realization of a wide range frequency synthesizer have run into serious stability problems, especially in transferring control between loop elements. Employing both a frequency synthesizer and data input recovery means, for example, on a single loop may increase the gain excessively. A narrow PLL bandwidth is desirable to decrease loop gain and may further serve to prevent jitter, but the tradeoff is that lock acquisition time increases as the bandwidth narrows.
Some prior patents have addressed, at least partially, the problem of clock recovery from random data input over a wide range of data frequencies. U.S. Pat. No. 4,375,693 to Kuhn employs a second order PLL having auto-ranging capability, but does not include a frequency synthesizer and, thus, provides only a coarse frequency acquisition (within one half octave). To compensate for this, the Kuhn PLL has a wider bandwidth and acquisition range, but that is often an undesirable feature, especially in high frequency environments and where jitter becomes excessive. The Kuhn device is also restricted in its recoverable clock frequencies because the phase comparator includes frequency division by 32.
U.S. Pat. No. 3,959,601 to Olevsky is specifically discussed and distinguished in the Kuhn Patent on the basis of its frequency synthesizer means to modulate the data signal to higher frequencies. The range of recoverable frequencies is comparatively limited. The specification contemplates operation only up to 12.95 MHz and the presence of up counter 14 effectively limits the top frequency to only 100 MHz. Further, the frequency synthesizer does not share a common VCO with a clock recovery PLL.
Other patents, such as U.S. Pat. No. 4,215,245 to Bellisio, are addressed to entirely different problems, but include in their circuitry an auto-ranging wide range VCO means. However, none of these references are known to suggest the use of such a VCO means shared between a frequency synthesizer and a clock recovery PLL.
Further, in many data communications systems, it is particularly desirable to have as wide and high a frequency range of recoverable clock signals as possible. Unfortunately, in many current commercially available VCO's there is a tradeoff between the VCO tunable range and the maximum frequency which can be produced. For example, VCO's having a top frequency of 50 MHz may typically have a tunable range of 45 MHz, down to 5 MHz. However, VCO's having a top frequency of 250 MHz are usually only tunable down to 125 MHz. Thus, as the top frequency increases, the ratio of the top to bottom frequencies decreases. This tradeoff often requires at least extremely complex circuitry having, for example, signal mixing and filtering to achieve a clock recovery range for high top frequency systems also having an extended range.
It is therefore an object of the present invention to provide a means for clock signal recovery from variable rate data streams over a wide range of frequencies.
Another object of the present invention is the provision of a clock recovery circuit operable at high frequencies and having a short lock acquisition time.
A further object of the present invention is to provide clock recovery from non return to zero input data over a large range of data rates.
A still further object is the provision of a clock recovery means wherein system stability is maintained in a smooth transfer of VCO control between a wide range frequency synthesizer means and a clock recovery PLL.
Yet another object is to provide a wide range clock recovery circuit having PLL means and frequency synthesizer means for programming the VCO of that PLL means and with single loop realization without mixing and filtering.
Yet still another object is the provision of a clock recovery circuit tunable over a wide frequency range and at high frequencies wherein the PLL bandwidth may be very narrow and yet provide short acquisition time by inputting an initial estimate of the clock frequency.
These and other objects of the present invention are attained in the provision of a clock signal recovery circuit for digital data communications having data input means, phase lock loop (PLL) clock recovery means, and wide range frequency synthesizer means. The PLL means and frequency synthesizer means share control of a single wide range VCO means which includes a narrow range VCO with frequency divider means and auto-ranging means for permitting single loop realization. Coarse tuning of the data rate may be achieved by user programming of an approximate data frequency value into the wide range frequency synthesizer loop which initially controls the VCO output frequency. Fine tuning is achieved by the PLL directly when the frequency synthesizer brings the difference between the wide range VCO frequency and the actual data rate to within the PLL bandwidth. Frequency synthesizer control of the wide range VCO is disabled during fine tuning.
The present invention permits the utilization of a narrow bandwidth PLL in a wide range clock recovery circuit. Thus, the PLL means can reduce jitter and provide better overall circuit stability in high frequency applications. In order to maintain short acquisition time in wide range applications, a frequency synthesizer means is provided for initially controlling the VCO means also utilized by the PLL means. The frequency synthesizer means responds to user input signals which represent estimates of the input data rate to control the output frequency of the shared VCO means. If this frequency estimate is accurate to within the seizure bandwidth of the PLL means, when the frequency synthesizer means causes the VCO means to reach that estimated frequency the PLL means seizes control of the VCO means for fine tuning of that estimated frequency and disables control by the frequency synthesizer means.
To permit single loop realization of such a wide range clock recovery circuit at high frequencies, a wide range VCO means is provided having an auto-ranging means. The narrow range VCO means may provide the highest frequency "window" or range of tunable frequencies. If, for example, the input data rate or the frequency synthesizer means' estimate of that data rate is less than any frequency in that window, then the auto-ranging means divides down the narrow range VCO frequency by some predetermined factor so as to create a lower frequency window and then checks to see if the estimated or input data rate is within this range. When the appropriate frequency range is found, the VCO means is tuned to output the estimated frequency.
Other objects, advantages, and novel features of the present invention will become apparent when considering the following detailed description of the preferred embodiment in conjunction with the drawings.